Relatively large copper lines in electronic equipment, for example, in a printed wiring board (“PWB”), are typically formed by a process including lamination, photolithography, and wet etching. A wet etch is generally isotropic. Therefore, such processes are usually limited to the formation of relatively wide copper lines so that undercutting of copper is small relative to the amount of metal in the copper line.
Copper lines in printed wiring boards generally have dimensions not less than about 0.5 mm wide and about 20 microns (μm) thick. Typically, more than 30 percent of copper deposited during formation of copper lines in stripped. The resulting copper-contaminated etch solution is a waste product requiring expensive disposal. Significantly larger quantities of copper are consumed in the PWB industry compared to the integrated circuit chip industry. PWB production is acutely price sensitive.
Another method of patterning copper lines, that was also commonly used for making small lines until the invention of the damascene process, is through-resist plating. In this technique, a metal seed layer is first deposited to cover completely a base plane substrate, resist is applied over the seed layer, and areas to be plated-up are optically exposed and developed (wherein the resist is removed to expose copper seed at the base). Then, during electroplating, metal is deposited only in the exposed and developed areas. In such a technique, copper can be plated controllably only to the thickness of the resist. If additional copper is plated, it is no longer confined by the walls of the lines defined by the resist, and will tend to grow conformally and encroach into other lines due to plating both up and sideways. Also, in this technique, the plating solution contacts the resist. As a result of leaching of organic electroactive contamination from the resist, the lifetime of the plating solution is often reduced, adding cost to the overall process. A damascene process is well suited for producing lines of small depth (or height or thickness) in features having high aspect ratio but would be prohibitively expensive for thick copper layers due to the high cost of removing copper from the insulating dielectric surface (“field”). In a damascene process, copper plates onto the field area to a thickness corresponding to the desired height (or thickness) of the wiring line, and all of this excess copper must be removed by chemical mechanical planarization in order to form the copper line.
Thus, none of these techniques is ideally suited to the production of large copper lines, and each incurs considerable costs associated with consumed material and waste disposal. Therefore, it would be desirable to have a technique for plating copper that would create relatively thick wires without the need to remove a large amount of copper, and that would avoid electrolyte contamination associated with through-resist plating, allowing for longer plating bath lifetimes. Preferably, a technique for forming large copper lines would not have to be defined through etching of trenches in a dielectric.